Two considerations weigh very heavily in the design of semiconductor integrated circuits: operational performance and conservation of area within the integrated circuit (IC) or `chip`. Many circuit designs that provide outstanding performance must be rejected because of an `area penalty`, i.e. an increase in the layout area on the IC which is required to implement the circuit design. Conversely, circuit designs which offer substantial reductions in IC area are often rejected because of inadequate operating performance. Many of the patented advances in IC circuit design are those in which new paradigms and approaches are introduced in order to satisfy these seemingly conflicting objectives of performance and conservation of area.
Maximization of performance and conservation of IC area weigh very heavily in the design and layout of circuitry for memory ICs, especially dynamic random access memories (DRAMs). Among such circuitry are the wordline driver circuits for a memory. The primary function of a wordline driver circuit is to activate selected memory cells by raising or lowering the voltage on a wordline. A wordline is a conductor which is required to have long length to extend across all or a substantial part of a memory array to provide access to as many as multiple thousands of memory cells. Both the long length of the wordline and its use as the gate conductor for a great number of memory cells result in the wordline having high capacitance. Consequently, the wordline driver circuit must provide large current in order to drive the wordline between signal levels. In each new generation of DRAMs, continued expected increases in the scale of integration will require wordline conductors to extend to proportionally even greater lengths than before and to serve greater numbers of memory cells. Consequently, the increased wordline capacitance will require wordline driver circuits to have even greater device efficiency.
The ever-increasing scale of integration of ICs, especially DRAMs, requires that memory arrays be configured with vast numbers of wordlines, typically multiple thousands of wordlines per array. In addition, the available array of the IC is desirably configured in multiple banking units, each banking unit including a separate memory array, to more efficiently utilize the IC area. A wordline driver circuit must be provided for each of the multiple thousands of wordlines of a memory array. Hence, the area required by the wordline driver circuit can be a critical limitation to the utilization of the IC area. Accordingly, a layout for a wordline driver circuit is needed which provides superior operating performance while occupying less IC area than existing layouts.
To illustrate the background of the present invention, FIG. 1 is a diagram showing the layout of a simple wordline driver which is constructed of an insulated gate field effect transistor (IGFET) 10. With reference to FIG. 1, IGFET 10 includes an active area (AA1) in the semiconductor substrate and a gate conductor 14 which traverses the active area AA1 in the y-direction. On respective sides of the gate conductor 14 are a source (S) and a drain (D).
In order to provide desirably high current throughput through the wordline driver, the width to length ratio (W/L) of IGFET 10 should be high. As is apparent from FIG. 1, the width 12 of the IGFET 10 is the extent of the gate conductor 14 over the active area AA1 in the y-direction (from top to bottom of FIG. 1). The width of the gate conductor 14 determines the effective length (L.sub.eff) of IGFET 10. Thus, increasing the W/L ratio and the current throughput of the transistor can only be accomplished by decreasing the width of the gate conductor 14 (to decrease L.sub.eff of the IGFET 10) or by increasing the active area AA1 of the semiconductor substrate over which the gate conductor 14 extends in the y-direction. As apparent from FIG. 1, the linear layout of IGFET 10 requires an active area AA1 which is relatively long in the y-direction. More efficient utilization of area is needed.
FIG. 2 shows the layout for an IGFET 20 of a "two-fingered" type of wordline driver circuit. In this two-fingered layout, the gate conductor 26 extends, like prongs 22, 24 of a fork, in parallel conductors over the active area AA2. The prongs 22, 24 of the gate conductor 26 operate as a linear gate conductor which has been bent at the middle to traverse the same active area AA at two places. The source regions (S) of the transistor lie to the outside of the prongs 22, 24, while the drain region (D) lies between the prongs 22, 24. In the layout shown in FIG. 2, the extent of the active area AA2 in the y-direction is decreased relative to that of active area AA1 shown in FIG. 1. However, the extent of the active area AA2 in the x-direction is increased relative to that of AA1 (FIG. 1) to accommodate the parallel conductors and parallel source/drain/source arrangement of transistor elements. A still more area-conserving layout for a wordline driver is needed.
FIG. 3 shows a physical contour map for the gate conductors in a wordline driver circuit section of a DRAM IC which precedes the invention, but is not admitted to be prior art. FIG. 3 shows yet another possible design in which a gate conductor 32 of a wordline driver circuit is single-stranded. Each gate conductor 32 is "wiggled", i.e. shifted to one side or another on the substrate surface, in order to conserve IC area while enlarging source and drain contact areas 34, 36 to accommodate the formation of contact studs. The layout shown in FIG. 3 requires an active semiconductor area AA3 which extends less in the x-direction than the layouts shown in FIGS. 1 and 2, but still requires the active area AA3 to be long in the y-direction to accommodate long gate conductors 32.
One disadvantage associated with the layout shown in FIG. 3 is that conductors on the first wiring level (M0) of the IC above the gate conductors must be laid out in a pattern specifically designed to accommodate the "wiggled", i.e. shifting gate conductor patterns therein. Another disadvantage is that the wiggled layout shown in FIG. 3 results in a reduced number of contact points through which current can be supplied or output through source and drain terminals of each wordline driver circuit.
One problem which occurs in the design and layout of wordline driver circuits for each successive generation of DRAM is the nonscalability of channel lengths in p-type IGFET devices (PFETs). For example, with reference to FIG. 1, for a DRAM generation being scaled by 30% from a groundrule of 0.25 um in a first generation (a) to a groundrule of 0.175 um in generation (b), the device length L.sub.eff of the PFET, which is 0.45 um in generation (a), can only be scaled by 22% to 0.35 um in the later generation (b). In future generations, the PFET device length may be even less scalable than in this example.
The PFET device length L.sub.eff extends in the x-direction which is the direction in which adjacent wordlines of the array are spaced at critical intervals. In prior DRAM generations, a wordline driver layout such as that shown in FIG. 2, the required PFET device length has accommodated a "stagger-4" layout of wordline driver circuits and permitted 1 of 4 decoding. In a stagger-4 layout, groups of four wordline driver circuits are patterned parallel to each other within a given unit of active area extending in the x-direction. In the stagger-4 arrangement, the first group of four wordline driver circuits are "stacked" with a second group of four circuits which are placed adjacent to the first group but at a different location in the y-direction further away from the memory array.
It is desirable to maintain a stagger-4 layout and 1 of 4 decoding because such layout permits the extent of the wordline driver circuit in the y-direction to kept to a minimum. But this is only possible if the width in the x-direction of each group of four wordline driver circuits can be constrained within existing tolerances.
In designing a generation of DRAMs, if the width in the x-direction of wordline driver circuits cannot be constrained within tolerances, then a stagger-8 layout of wordline driver circuits will be required. In a stagger-8 layout, wordline driver circuits are arranged in parallel in groups of two circuits within a given unit of active area in the x-direction. In the stagger-8 arrangement, each group of two wordline driver circuits is "stacked" with second, third and fourth groups of two circuits, wherein each group is placed next to each other but at different locations extending away from the memory array. Consequently, a stagger-8 arrangement doubles the extent of the wordline driver circuits in the y-direction in relation to the stagger-4 arrangement.
As described above, the device length of PFETs cannot be linearly scaled. This leads to a proportional increase, for each successive generation of ICs, in the extent in the x-direction of wordline driver circuits which are constructed with PFETs. Unfortunately, for this reason, an existing layout arrangement such as that shown in FIGS. 2 or 3 would not accommodate a stagger-4 arrangement in DRAM generations smaller than 0.25 um because of the proportionally greater extent in the x-direction of the wordline driver circuits.
Absent the present invention, to be described in the following sections, a stagger-8 arrangement of drivers would be required.
U.S. Pat. No. 5,567,553 to Hsu et al. ("the '553 Patent") describes a two-gate field effect transistor (FET) structure which is designed to have shorter device gate length where the gate conductor overlays the active area of the semiconductor surface than where the gate conductor overlays shallow trench isolation (STI) areas. A phase edge pattern of a mask is used to form resist patterns which result in short device gate length patterns over the active semiconductor area. Opaque patterns are used to form resist patterns which result in long device gate length over the STI regions.
The purpose stated in the '553 Patent for defining gate conductor patterns which vary in device gate length with respect to relative position is to achieve a device threshold voltage Vt which stays the same regardless of the position of the gate conductor over the STI region or the active area. The '553 Patent neither teaches nor suggests defining a series of ring-shaped gate conductor patterns over a continuous area of active semiconductor, having a conductor width which need not vary with position, in order to increase the device gate width without increasing the amount of IC area consumed by a set of adjacent conductor patterns.
Accordingly, it is an object of the invention provide a layout for a wordline driver circuit which reduces the area occupied by the circuit on the IC.
Another object of the invention is to provide a layout for a wordline driver capable of driving increased current on the wordline.
Another object of the invention is to provide a layout for a wordline driver circuit which accommodates increased device length requirements.
Still another object of the invention is to provide a layout for a wordline driver circuit which permits maintaining a stagger-4 arrangement in successive DRAM generations.